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ltc3861-1 1 38611f typical a pplica t ion descrip t ion dual, multiphase step-down v oltage mode dc/dc controller with accurate current sharing the lt c ? 3861-1 is a dual polyphase ? synchronous step- down switching regulator controller for high current distributed power systems, digital signal processors, and other telecom and industrial dc / dc power supplies. it uses a constant- frequency voltage mode architecture combined with very low offset, high bandwidth error amplifiers and a remote output sense differential amplifier for excellent transient response and output regulation. the controller incorporates lossless inductor dcr current sensing to maintain current balance between phases and to provide overcurrent protection. the chip operates from a v cc supply between 3 v and 5.5 v and is designed for step- down conversion from v in between 3 v and 24 v to output voltages between 0.6 v and v cc C 0.5v. inductor current reversal is disabled during soft - start to safely power prebiased loads. the constant operating frequency can be synchronized to an external clock or linearly programmed from 250 khz to 2.25 mhz. up to six ltc3861-1 controllers can operate in parallel for 1-, 2-, 3-, 4-, 6- or 12- phase operation. the ltc3861-1 is pin- to- pin compatible with the ltc3860. it is available in a 32-pin 5 mm 5 mm qfn package. the ltc3861is a 36- pin qfn version of the ltc3861-1, which has dual differential output voltage sense amplifiers. fea t ures a pplica t ions n operates with power blocks, drmos or external gate drivers and mosfet s n constant-frequency voltage mode control with accurate current sharing n 0.75% 0.6v v oltage reference n differential remote output voltage sense amplifier n multiphase capabilityup to 12-phase operation n programmable current limit n safely powers a prebiased load n programmable or pll-synchronizable switching frequency up to 2.25mhz n lossless current sensing using inductor dcr or precision current sensing with sense resistor n v cc range: 3v to 5.5v n v in range: 3v to 24v n power good output voltage monitor n output voltage tracking capability n programmable soft-start n available in a 32-pin 5mm 5mm qfn package n high current distributed power systems n dsp, fpga and asic supplies n datacom and telecom systems n industrial power supplies l, lt , lt c , lt m , polyphase, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6144194, 5055767 vsnsout vsnsp vsnsn config v cc freq fb2 i lim2 fb1 comp1,2 ss1,2 vinsns in v logic v cc boost gnd tg ts bg run1,2 i lim1 isns1p isns1n isns2n isns2p ltc3861-1 pwm1 ltc4449 v in , 7v to 14v v in 0.47h sgnd clkin pwm2 180f 1f 0.22f 0.22f v cc v cc 0.22f 100pf 1nf 0.1f 1nf 13k 221 59k 2.87k 2.87k 20k 220pf v out v in , 7v to 14v v cc in v logic v cc boost gnd tg ts bg ltc4449 0.47h 0.22f 38611 ta01 330f 6 100f 4 v out 1.2v 60a i avg 20k 28.7k
ltc3861-1 2 38611f v cc voltage .................................................. C 0.3 v to 6v vinsns voltage ......................................... C 0.3 v to 30 v run voltage ................................................. C0.3 v to 6v isns 1p , isns 1n, isns 2p , isns 2n ........................... C 0.3 v to (v cc + 0.1 v) all other pins ................................ C 0.3 v to (v cc + 0.3 v) operating junction temperature range ( notes 2, 3) ............................................ C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (note 1) 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 sgnd uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1v cc fb1 comp1 vsnsout vsnsn vsnsp comp2 fb2 run1 i lim1 isns1p isns1n isns2n isns2p i lim2 run2 track/ss1 vinsns config sgnd i avg pgood1 pwmen1 pwm1 track/ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 t jmax = 125c, ja = 34c/w exposed pad (pin 33) is sgnd, must be soldered to pcb o r d er i n f orma t ion lead free finish tape and reel part marking* package description temperature range ltc3861euh-1#pbf ltc3861euh-1#trpbf 38611 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc3861iuh-1#pbf ltc3861iuh-1#trpbf 38611 32-lead (5mm 5mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ for more information on soldering profiles, go to: http://cds.linear.com/docs/packaging/linear_technology_surface_mount_products.pdf p in c on f igura t ion a bsolu t e m aximum r a t ings
ltc3861-1 3 38611f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25c (note 3). v cc = 5v, v run1,2 = 5v, v freq = 5v, v clkin = 0v, v fb = 0.6v, f osc = 0.6mhz, unless otherwise specified. symbol parameter conditions min typ max units v in v in range v cc = 5v l 3 24 v v cc v cc voltage range l 3 5.5 v i q input voltage supply current normal operation shutdown mode uvlo v run1,2 = 5v v run1,2 = 0v v cc < v uvlo 18 6 50 ma a ma v run run input threshold v run rising v run hysteresis 1.95 2.25 250 2.45 v mv i run run input pull-up current v run1,2 = 2.4v 1.5 a v uvlo undervoltage lockout threshold v cc rising v cc hysteresis l 100 3.0 v mv i ss soft-start pin output current v ss = 0v 2.5 a t ss(internal) internal soft-start time 1.5 ms v fb regulated feedback voltage C40c to 85c C40c to 125c l 595.5 594 600 600 604.5 606 mv mv ?v fb /?v cc regulated feedback voltage line dependence 3.0v < v cc < 5.5v 0.05 0.2 %/v i limit i lim pin output current v ilim = 0.8v 19 20 22 a power good v fb(ov) pgood/v fb overvoltage threshold v fb falling v fb rising 650 645 660 670 mv mv v fb(uv) pgood/v fb undervoltage threshold v fb falling v fb rising 530 540 555 550 mv mv v pgood(on) pgood pull-down resistance 15 60 i pgood(off) pgood leakage current v pgood = 5v 2 a t pgood pgood delay v pgood high to low 30 s error amplifier i fb fb pin input current v fb = 600mv C100 100 na i out comp pin output current sourcing sinking 1 5 ma ma a v(ol) open-loop voltage gain 75 db sr slew rate (note 4) 45 v/s f 0db comp unity-gain bandwidth (note 4) 40 mhz differential amplifier a v differential amplifier voltage gain v vsnsn = 0v l 1.007 1 0.993 v/v v os input referred offset v vsnsn = 0v C2 2 mv f 0db da unity-gain crossover frequency (note 4) 40 mhz i out(sink) maximum sinking current diffout = 1.2v 100 a i out(source) maximum sourcing current diffout = 1.2v 500 a v snsout(max) maximum output voltage 4 v current sense amplifier v isense(max) maximum differential current sense voltage (v isnsp -v isnsn ) 50 mv a v(isense) voltage gain 18.5 v/v v cm(isense) input common mode range C0.3 v cc C 0.5 v
ltc3861-1 4 38611f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25c (note 3). v cc = 5v, v run1,2 = 5v, v freq = 5v, v clkin = 0v, v fb = 0.6v, f osc = 0.6mhz, unless otherwise specified. symbol parameter conditions min typ max units i isense sense pin input current v cm = 1.5v 100 na v os current sense input referred offset C40c to 125c l C1.25 1.25 mv oscillator and phase-locked loop f osc oscillator frequency v clkin = 0v v freq = 0v v freq = 5v l l 360 540 400 600 440 660 khz khz v clkin = 5v r freq < 24.9k r freq = 36.5k r freq = 48.7k r freq = 64.9k r freq = 88.7k 200 600 1 1.45 2.1 khz khz mhz mhz mhz maximum frequency minimum frequency 3 0.25 mhz mhz i freq freq pin output current v freq = 0.8v 18.5 20 21.5 a t clkin(hi) clkin pulse width high v clkin = 0v to 5v 100 ns t clkin(lo) clkin pulse width low v clkin = 0v to 5v 100 ns r clkin clkin pull-up resistance 13 k v clkin clkin input threshold v clkin falling v clkin rising 1.2 2 v v v freq freq input threshold v clkin = 0v v freq falling v freq rising 1.5 2.5 v v v ol(clkout) clkout low output voltage i load = C500a 0.2 v v oh(clkout) clkout high output voltage i load = 500a v cc C 0.2 v 2 - 1 channel 1-to-channel 2 phase relationship v phsmd = 0v v phsmd = float v phsmd = v cc 180 180 120 deg deg deg clkout - 1 clkout-to-channel 1 phase relationship v phsmd = 0v v phsmd = float v phsmd = v cc 60 90 240 deg deg deg pw m /p wmen outputs pwm pwm output high voltage i load = 500a l 4.5 v pwm output low voltage i load = C500a l 0.5 v pwm output current in hi-z state 5 a pwm maximum duty cycle 91.5 % pwmen pwmen output high voltage i load = 1ma l 4.5 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 34c/w) note 3: the ltc3861-1 is tested under pulsed load conditions such that t j t a . the ltc3861-1e is guaranteed to meet performance specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3861-1i is guaranteed over the full C40c to 125c operating junction temperature range. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistors and other environmental factors. note 4: guaranteed by design.
ltc3861-1 5 38611f typical p er f ormance c harac t eris t ics load step transient response (4-phase using tda21220 drmos) line step transient response (2-phase using ltc4449) efficiency vs load current feedback voltage v fb vs temperature load step transient response (single phase using ltc4449) load step transient response (2-phase using d12s1r845a power block) load step transient response (3-phase using fdmf6707b drmos) load current (a) 0 efficiency (%) 90 95 85 80 75 70 65 60 20 30 50 10 40 60 70 55 50 100 38611 g07 v in = 12v v out = 1.2v 2-phase, ltc4449 f sw = 300khz 20s/div 38611 g01 v out 50mv/div ac-coupled v in = 12v v out = 1.2v i load step = 3a to 18a to 3a f sw = 300khz i l 10a/div 40s/div 38611 g02 i load 20a/div v out 50mv/div ac-coupled v in = 12v v out = 1.2v i load step = 0a to 20a to 0a f sw = 300khz i l1 10a/div i l2 10a/div 50s/div 38611 g03 v out 50mv/div ac-coupled v in = 12v v out = 1.2v i load step = 4a to 20a to 4a f sw = 400khz i load 20a/div 50s/div 38611 g04 v out 100mv/div ac-coupled v in = 12v v out = 1.2v i load step = 0a to 30a to 0a f sw = 500khz external clock i l2 10a/div i l1 10a/div i l3 10a/div 40s/div 38611 g05 v out 50mv/div ac-coupled v in = 12v v out = 1v i load step = 40a to 80a to 40a f sw = 500khz external clock i load 40a/div 20s/div 38611 g06 v in 10v/div v out 50mv/div ac-coupled v in = 7v to 14v in 20s v out = 1.2v i load = 20a f sw = 300khz i l1 10a/div i l2 10a/div load step transient response (2-phase using ltc4449) temperature (c) ?50 regulated v fb voltage (v) 600.50 600.75 600.25 600.00 0 25 75 ?25 50 100 125 150 599.75 599.50 601.00 38611 g09 efficiency vs load current 0 86 90 70 82 78 20 40 10 90 30 50 80 60 100 74 70 94 88 92 84 80 76 72 96 38611 g08 load current (a) efficiency (%) v in = 12v, v out = 1v 4-phase tda21220 drmos f sw = 500khz external clock
ltc3861-1 6 38611f typical p er f ormance c harac t eris t ics coincident tracking (single phase using fdmf6707b drmos) ratiometric tracking (single phase using fdmf6707b drmos) start-up response into a 300mv prebiased output (single phase using fdmf6707b drmos) initial 7-cycle nonsynchronous start-up (single phase using fdmf6707b drmos) start-up into a short (single phase using fdmf6707b drmos) start-up response (2-phase using ltc4449) start-up response (3-phase using fdmf6707b drmos) soft-start start-up response (2-phase using d12s1r845a power block) regulated v fb vs supply voltage supply voltage (v) 3 596 regulated v fb voltage (v) 598 600 602 604 4 5 38611 g10 6 2ms/div 38611 g14 v in = 12v v out = 1.8v f sw = 500khz external clock 3.3v tracking signal v out 500mv/div 2ms/div 38611 g15 v in = 12v v out = 1.8v f sw = 500khz external clock 3.3v tracking signal v out 500mv/div 200s/div 38611 g16 v out 500mv/div v in = 12v v out = 1.8v f sw = 500khz external clock pwm 2v/div i l 10a/div 5s/div 38611 g17 v out 500mv/div v in = 12v v out = 1.8v 300mv prebiased output f sw = 500khz external clock pwm 2v/div i l 10a/div 10ms/div 38611 g18 v out 500mv/div v in = 12v v out = 1.8v f sw = 500khz external clock pwm 2v/div track/ss 500mv/div i l 20a/div 5ms/div 38611 g13 v out 200mv/div v in = 12v v out = 1.2v 0.1f capacitor on track/ss1 f sw = 400khz 500s/div 38611 g11 v out 1v/div v in = 12v v out = 1.2v r load 50m i l2 10a/div i l1 10a/div v run 5v/div internal soft-start 500s/div 38611 g12 v out 500mv/div v in = 12v v out = 1v r load = 30m f sw = 500khz i l2 10a/div i l3 10a/div i l1 10a/div internal soft-start
ltc3861-1 7 38611f 128-cycle overcurrent counter (single phase using fdmf6707b drmos) typical p er f ormance c harac t eris t ics freq pin current vs temperature 600khz preset frequency vs temperature 400khz preset frequency vs temperature quiescent current vs temperature shutdown quiescent current vs temperature oscillator frequency vs r freq overcurrent threshold vs temperature i lim pin current vs temperature 50s/div 38611 g19 v out 500mv/div v in = 12v v out = 1.8v f sw = 500khz external clock pwm 2v/div track/ss 200mv/div i l 20a/div r freq (k) 0 oscillator frequency (mhz) 40 80 100 38611 g20 0.9 2.1 2.3 2.5 0.5 1.7 1.3 0.7 1.9 0.1 0.3 1.5 1.1 20 60 120 temperature (c) ?50 current sense voltage (mv) 25 30 35 20 15 50 0 100 150 10 5 40 38611 g21 i lim = 1.2v i lim = 800mv temperature (c) ?50 i lim pin current (a) 20.0 20.2 20.4 100 19.8 19.6 0 50 150 19.4 19.2 20.6 38611 g22 temperature (c) ?50 freq pin current (a) 20.0 20.2 20.4 100 19.8 19.6 0 50 150 19.4 19.0 19.2 20.6 38611 g23 temperature (c) ?50 oscillator frequency (khz) 610 605 615 600 595 590 0 25 75 ?25 50 100 125 150 585 580 620 38611 g24 temperature (c) ?50 385 390 380 375 50 0 100 150 370 365 395 oscillator frequency (khz) 38611 g25 temperature (c) ?50 quiescent current (ma) 22 125 20 18 16 12 0 50 ?25 25 75 100 150 14 10 24 38611 g26 v in = 6v v cc = 5v run1 = run2 = 5v temperature (c) ?50 shutdown current (a) 32 33 125 31 30 0 50 ?25 25 75 100 150 29 28 34 38611 g27 v in = 6v v cc = 5v
ltc3861-1 8 38611f typical p er f ormance c harac t eris t ics track/ss current vs track/ss voltage track/ss pull-up current vs temperature run threshold vs temperature run pull-up current vs temperature shutdown quiescent current vs supply voltage supply voltage (v) 0 0 shutdown current (a) 10 20 30 1 2 3 4 40 5 15 25 35 65 38611 g28 temperature (c) ?50 run pin voltage (v) 2.10 2.15 2.20 125 2.05 2.00 0 50 ?25 25 75 100 150 1.95 1.90 2.25 38611 g29 rising falling temperature (c) ?50 1.8 2.0 1.6 1.4 50 0 100 150 1.2 1.0 2.2 run pin current (a) 38611 g30 track/ss pin voltage (v) 0 track/ss pin current (a) ?1.0 ?0.5 0 ?1.5 ?2.0 2 4 1 3 5 ?2.5 ?3.0 0.5 38611 g31 temperature (c) ?50 2.2 track/ss pin current (a) 2.4 2.6 2.8 0 50 150 100 3.0 2.3 2.5 2.7 2.9 38611 g32
ltc3861-1 9 38611f v cc (pin 1): chip supply voltage. bypass this pin to gnd with a capacitor (0.1 f to 1 f ceramic) in close proximity to the chip. fb1 (pin 2), fb2 (pin 8): error amplifier inverting input. fb1 or fb2 can be connected to vsnsout via a resistor divider for remote v out sensing. the bottom of the divider should be connected to the sgnd pin of the ic. the other fb, when used, is typically connected to the second v out via a resistor divider, also terminated at the ic sgnd pin. comp1 (pin 3), comp2 (pin 7): error amplifier outputs. pwm duty cycle increases with this control voltage. the error amplifiers in the ltc3861-1 are true operational amplifiers with low output impedance. as a result, the outputs of two active error amplifiers cannot be directly connected together! for multiphase operation, connecting the fb pin on an error amplifier to v cc will three-state the output of that amplifier. multiphase operation can then be achieved by connecting all of the comp pins together and using one channel as the master and all others as slaves. when the run pin is low, the respective comp pin is actively pulled down to ground. vsnsout (pin 4): differential amplifier output. connect to fb1 or fb2 with a resistive divider and compensation network for remote v out sensing. vsnsn ( pin 5): differential sense amplifier inverting input . connect this pin to sense ground at the output load. vsnsp (pin 6): differential sense amplifier noninverting input. connect this pin to v out at the output load. freq (pin 10): frequency set/select pin. this pin sources 20a current. if clkin is high or floating, then a resistor between this pin and sgnd sets the switching frequency. if clkin is low, the logic state of this pin selects an internal 600khz or 1mhz preset frequency. clkin (pin 11): external clock synchronization input. applying an external clock between 250 khz to 2.25mhz will cause the switching frequency to synchronize to the clock. clkin is pulled high to v cc by a 50 k internal resis- tor. the rising edge of the clkin input waveform will align with the rising edge of pwm 1 in closed-loop operation. if clkin is high or floating, a resistor from the freq pin to sgnd sets the switching frequency. if clkin is low, the freq pin logic state selects an internal 600 khz or 1mhz preset frequency. clkout (pin 12): digital output used for daisychain - ing multiple ltc3861-1 ics in multiphase systems. the phsmd pin voltage controls the relationship between ch1 and ch2 as well as between ch1 and clkout. when both run pins are driven low, the clkout pin is actively pulled up to v cc . phsmd (pin 13): phase mode pin. the phsmd pin volt- age programs the phase relationship between ch1 and ch2 rising pwm signals, as well as the phase relationship between ch1 pwm signal and clkout. floating this pin or connecting it to either v cc or sgnd changes the phase relationship between ch1, ch2 and clkout. isns1n (pin 21), isns2n (pin 20): current sense am- plifier (C) input. the (C) input to the current amplifier is normally connected to the respective v out at the inductor. isns1p (pin 22), isns2p (pin 19): current sense ampli- fier (+) input. the (+) input to the current sense amplifier is normally connected to the midpoint of the inductors parallel rc sense circuit or to the node between the induc- tor and sense resistor if using a discrete sense resistor. i lim1 (pin 23), i lim2 (pin 18): current comparator sense voltage limit selection pin. connect a resistor from this pin to sgnd. this pin sources 20a . the resultant voltage sets the threshold for over current protection. run1 (pin 24), run2 (pin 17): run control inputs. a voltage above 2.25 v on either pin turns on the ic. how- ever, forcing either of these pins below 2 v causes the ic to shut down that particular channel. there are 1.5a pull-up currents for these pins. pwm 1 (pin 25), pwm 2 (pin 16): ( top ) gate signal out- put. this signal goes to the pwm or top gate input of the external gate driver or integrated driver mosfet. this is a three-state compatible output. pwmen 1 (pin 26), pwmen2 (pin 15): enable pin for non-three-state compatible drivers. this pin has an in- ternal open-drain pull-up to v cc . an external resistor to sgnd is required. this pin is low when the corresponding pwm pin is high impedance. p in func t ions
ltc3861-1 10 38611f p in func t ions pgood1 (pin 27), pgood2 (pin 14): power good indi- cator output for each channel. open-drain logic out that is pulled to sgnd when either channel output exceeds a 10% regulation window, after the internal 30 s power bad mask timer expires. i avg (pin 28): average current output pin. a capacitor tied to ground from this pin stores a voltage proportional to the instantaneous average current of the master when multiple outputs are paralleled together in a master-slave configuration. only the master phase contributes infor- mation to this average through an internal resistor when in current sharing mode. the i avg pin ignores channels configured for independent operation, hence the pin should be connected to sgnd when the controller drives independent outputs. sgnd (pin 29, exposed pad pin 33): signal ground. pins 29 and 33 are electrically connected internally. the exposed pad must be soldered to the pcb ground for rated thermal performance. all soft-start, small-signal and compensation components should return to sgnd. config (pin 30): line feedforward configuration pin. this pin allows the user to configure the multiplier to achieve accurate modulator gain over varying v in and switching frequencies. this pin can be connected to v cc or sgnd. an internal resistor will pull this pin to sgnd when it is floated. vinsns (pin 31): v in sense pin. connects to the v in power supply to provide line feedforward compensation. a change in v in immediately modulates the input to the pwm comparator and changes the pulse width in an in- versely proportional manner, thus bypassing the feedback loop and providing excellent transient line regulation. an external lowpass filter can be added to this pin to prevent noisy signals from affecting the loop gain. track/ss1 (pin 32), track/ss2 (pin 9): combined soft-start and tracking inputs. for soft-start operation, connecting a capacitor from this pin to ground will control the voltage ramp at the output of the power supply. an internal 2.5 a current source will charge the capacitor and thereby control an extra input on the reference side of the error amplifier. for tracking operation, this input allows the start-up of a secondary output to track a primary output according to a ratio established by a resistor divider from the primary output to the secondary error amplifier track pin. for coincident tracking of both outputs at start-up, a resistor divider with values equal to those connected to the secondary vsnsp pin from the secondary output should be used to connect the secondary track input from the primary output. this pin is internally clamped to 1.2 v, and is used to communicate over current events in a master-slave configuration.
ltc3861-1 11 38611f func t ional diagram 22 isns1p 21 isns1n 20 23 18 28 isns2n i avg i lim2 i lim1 20a 21a 20a 10 freq 13 phsmd 12 clkout 11 16 clkin 38611 bd oc1 noc1 oc2 noc2 19 isns2p x18.5 x18.5 8 fb2 7 comp2 9 track/ss2 ea2 ref ref 2 fb1 32 track/ss1 3 comp1 ea1 + + ? + + ? + ? + ? 5 vsnsn 24 run1 100k v cc 1.5a 1.5a v cc 17 run2 6 vsnsp 4 vsnsout da s v fb1 i lim1 v fb2 i lim2 s master/slave/ independent sd/uvlo 27 pgood1 v fb1 v fb2 14 pgood2 ramp/slope/ feedforward pgood logic oc1 oc2 ov1 ov2 noc1 noc2 pwm2 31 vinsns 25 pwm1 15 pwmen2 26 pwmen1 pll/vco bg/bias v cc v cc v cc 100k v cc 1 v cc 29 sgnd 30 config + +
ltc3861-1 12 38611f o pera t ion (refer to functional diagram) main control architecture the ltc3861-1 is a dual-channel/dual-phase, constant- frequency, voltage mode controller for dc/dc step-down applications. it is designed to be used in a synchronous switching architecture with external integrated - driver mos - fets or power blocks, or external drivers and n-channel mosfets using single wire three-state pwm interfaces. the controller allows the use of sense resistors or lossless inductor dcr current sensing to maintain current balance between phases and to provide overcurrent protection. the operating frequency is selectable from 250 khz to 2.25mhz. to multiply the effective switching frequency, multiphase operation can be extended to 3, 4, 6, or 12 phases by paralleling up to six controllers. in single or 3-phase operation, the 2 nd or 4 th channel can be used as an independent output. the output of the differential amplifier is connected to the error amplifier inverting input ( fb) through a resistor divider. the remote sense differential amplifier output (v snsout ) provides a signal equal to the differential voltage (v snsp C v snsn ) sensed across the output capacitor, but re-referenced to the local ground ( sgnd). this permits accurate voltage sensing at the load, without regard to the potential difference between its ground and local ground. in the main voltage mode control loop, the error ampli- fier output ( comp) directly controls the converter duty cycle in order to drive the fb pin to 0.6 v in steady state. dynamic changes in output load current can perturb the output voltage. when the output is below regulation, comp rises, increasing the duty cycle. if the output rises above regulation, comp will decrease, decreasing the duty cycle. as the output approaches regulation, comp will settle to the steady-state value representing the step- down conversion ratio. in normal operation, the pwm latch is set high at the begin- ning of the clock cycle ( assuming comp > 0.5 v). when the ( line feedforward compensated) pwm ramp exceeds the comp voltage, the comparator trips and resets the pwm latch. if comp is less than 0.5 v at the beginning of the clock cycle, as in the case of an overvoltage at the outputs, the pwm pin remains low throughout the entire cycle. when the pwm pin goes high it has a minimum on-time of approximately 20 ns and a minimum off-time of approximately one-twelth the switching period. current sharing in multiphase operation, the ltc3861-1 also incorporates an auxiliary current sharing loop. inductor current is sampled each cycle. the masters current sense amplifier output is averaged at the i avg pin. a small capacitor con- nected from i avg to gnd (typically 100 pf) stores a voltage corresponding to the instantaneous average current of the master. each phase integrates the difference between its current and the masters. within each phase the integrator output is proportionally summed with the system error amplifier voltage ( comp), adjusting that phases duty cycle to equalize the currents. when multiple ics are daisychained the i avg pins must be connected together . when the phases are operated independently, the i avg pin should be tied to ground. figure 1 shows a transient load step with current sharing in a 3-phase system. figure 1. mismatched inductor load step transient response (3-phase using fdmf6707b drmos) overcurrent protection the current sense amplifier outputs also connect to overcur - rent ( oc) comparators that provide fault protection in the case of an output short. when an oc fault is detected for 128 consecutive clock cycles, the controller three-states the pwm output, resets the soft-start capacitor, and waits for 32768 clock cycles before attempting to start up again. the 128 consecutive clock cycle counter has a 7- cycle hysteresis window, after which it will reset. the ltc3861-1 also provides negative oc ( noc) protection by preventing 50s/div 38611 f01 v out 100mv/div ac-coupled v in = 12v v out = 1v i load step = 0a to 30a to 0a f sw = 500khz external clock i l1 (l= 0.47h) 10a/div i l2 (l= 0.25h) 10a/div i l3 (l= 0.47h) 10a/div
ltc3861-1 13 38611f turn-on of the bottom mosfet during a negative oc fault condition. in this condition, the bottom mosfet will be turned on for 20 ns every eight cycles to allow the driver ic to recharge its topside gate drive capacitor. the negative oc threshold is equal to C3/4 the positive oc threshold. see the applications information section for guidelines on setting these thresholds. excellent transient response the ltc3861-1 error amplifiers are true operational ampli- fiers, meaning that they have high bandwidth, high dc gain, low offset and low output impedance. their bandwidth, when combined with high switching frequencies and low- value inductors, allows the compensation network to be optimized for very high control loop crossover frequencies and excellent transient response. the 600 mv internal ref- erence allows regulated output voltages as low as 600mv without external level-shifting amplifiers. line feedforward compensation the ltc3861-1 achieves outstanding line transient re- sponse using a feedforward correction scheme which instantaneously adjusts the duty cycle to compensate for changes in input voltage, significantly reducing output overshoot and undershoot. it has the added advantage of making the dc loop gain independent of input voltage. figure 2 shows how large transient steps at the input have little effect on the output voltage. remote sense differential amplifier the ltc3861-1 includes a low offset, unity gain, high bandwidth differential amplifier for differential output sensing. output voltage accuracy is significantly improved by removing board interconnection losses from the total error budget. the ltc3861-1 differential amplifier has a typical output slew rate of 45v/s, bandwidth of 40mhz, input referred offset < 2 mv and a typical maximum output voltage of v cc C 1 v. the amplifier is configured for unity gain, meaning that the differential voltage between v snsp and v snsn is translated to v snsout , relative to sgnd. shutdown control using the run pins the two channels of the ltc3861-1 can be independently enabled using the run1 and run2 pins. when both pins are driven low, all internal circuitry, including the internal reference and oscillator, are completely shut down. when the run pin is low, the respective comp pin is actively pulled down to ground. in a multiphase operation when the comp pins are tied together, the comp pin is held low until all the run pins are enabled. this ensures a synchronized start-up of all the channels. a 1.5 a pull-up current is provided for each run pin internally. the run pins remain high impedance up to v cc . undervoltage lockout to prevent operation of the power supply below safe in- put voltage levels, both channels are disabled when v cc is below the undervoltage lockout ( uvlo) threshold (2.9 v falling, 3 v rising). if a run pin is driven high, the ltc3861-1 will start up the reference to detect when v cc rises above the uvlo threshold, and enable the appropriate channel. overvoltage protection if the output voltage rises to more than 10% above the set regulation value, which is reflected as a v fb voltage of 0.66 v or above, the ltc3861-1 will force the pwm output low to turn on the bottom mosfet and discharge the output. normal operation resumes once the output is back within the regulation window. however, if the re- verse current flowing from v out back through the bottom o pera t ion (refer to functional diagram) figure 2. 20s/div 38611 f02 v in 10v/div v out 50mv/div ac-coupled v in = 7v to 14v in 20s v out = 1.2v i load = 20a f sw = 300khz i l1 10a/div i l2 10a/div
ltc3861-1 14 38611f power mosfet to pgnd is greater than 3/4 the positive oc threshold, the noc comparator trips and shuts off the bottom power mosfet to protect it from being destroyed. this scenario can happen when the ltc3861-1 tries to start into a precharged load higher than the ov threshold. as a result, the bottom switch turns on until the amount of reverse current trips the noc comparator threshold. nonsynchronous start-up and prebiased output load the ltc3861-1 will start up with seven cycles of nonsynchronous operation before switching over to a forced continuous mode of operation. the pwm output will be in a three-state condition until start-up. the controller will start the seven nonsynchronous cycles if it is not in an overcurrent or prebiased condition, and if the comp pin voltage is higher than 500 mv, or if the track/ss pin voltage is higher than 580 mv. during the seven nonsynchronous cycles the pwm latch is set high at the beginning of the clock cycle, if comp > 0.5 v, causing the pwm output to transition from three-state to v cc . the latch is reset when the pwm ramp exceeds the comp voltage, causing the pwm output to transition from v cc to three -state followed immediately by a 20 ns three-state to ground pulse. the 7- cycle nonsynchronous mode of operation is enabled at initial start-up and also during a restart from a fault condition. in multiphase operation, where all the track/ss should be connected together, an overcurrent event on one channel will discharge the soft-start capacitor. after 32768 cycles, it will synchronize the restart of all channels in to the nonsynchronous mode of operation. the ltc3861-1 can safely start-up into a prebiased output without discharging the output capacitors. a prebias is detected when the fb pin voltage is higher than the track/ss or the internal soft-start voltage. a prebiased condition will force the comp pin to be held low, and will three-state the pwm output. the prebiased condition is cleared when the track/ ss or the internal soft- start voltage is higher than the fb pin voltage or 580 mv, whichever is lower. if the output prebias is higher than the ov threshold then the pwm output will be low, which will pull the output back in to the regulation window. internal soft-start by default, the start-up of each channels output voltage is normally controlled by an internal soft-start ramp. the internal soft-start ramp represents a noninverting input to the error amplifier. the fb pin is regulated to the lower of the error amplifier s three noninverting inputs ( the internal soft- start ramp for that channel, the track/ ss pin or the internal 600mv reference). as the ramp volt- age rises from 0 v to 0.6 v over approximately 2 ms, the output voltage rises smoothly from its prebiased value to its final set value. soft-start and tracking using track/ss pin the user can connect an external capacitor greater than 10nf to the track/ss pin for the relevant channel to increase the soft-start ramp time beyond the internally set default. the track/ss pin represents a noninverting input to the error amplifier and behaves identically to the internal ramp described in the previous section. an internal 2.5a current source charges the capacitor, creating a voltage ramp on the track/ss pin. the track/ss pin is internally clamped to 1.2 v. as the track/ss pin voltage rises from 0 v to 0.6 v, the output voltage rises smoothly from 0v to its final value in: c ss f ? 0.6v 2.5a seconds alternatively, the track/ss pin can be used to force the start-up of v out to track the voltage of another supply. typically this requires connecting the track/ss pin to an external divider from the other supply to ground ( see the applications information section). it is only possible to track another supply that is slower than the internal soft-start ramp. the track/ss pin also has an internal open-drain nmos pull-down transistor that turns on to reset the track/ss voltage when the channel is shut down (run = 0 v or v cc < uvlo threshold) or during an oc fault condition. in multiphase operation, one master error amplifier is used to control all of the pwm comparators. the fb pins for the unused error amplifiers are connected to v cc in order to three-state these amplifier outputs and the comp pins are connected together. when the fb pin is tied to v cc , the internal 2.5 a current source on the track/ss pin o pera t ion (refer to functional diagram)
ltc3861-1 15 38611f is disabled for that channel. the track/ss pins should also be connected together so that the slave phases can detect when soft-start is complete and to synchronize the nonsynchronous mode of operation. frequency selection and the phase- locked loop ( pll) the selection of the switching frequency is a trade-off between efficiency, transient response and component size. high frequency operation reduces the size of the inductor and output capacitor as well as increasing the maximum practical control loop bandwidth. however, efficiency is generally lower due to increased transition and switching losses. the ltc3861-1s switching frequency can be set in three ways: using an external resistor to linearly program the frequency, synchronizing to an external clock, or simply selecting one of two fixed frequencies (400khz and 600khz). table 1 highlights these modes. table 1. frequency selection clkin pin freq pin frequency clocked r freq to gnd 250khz to 2.25mhz high or float r freq to gnd 250khz to 2.25mhz low low 400khz low high 600khz no external pll filter is required to synchronize the ltc3861-1 to an external clock. applying an external clock signal to the clkin pin will automatically enable the pll with internal filter. constant-frequency operation brings with it a number of benefits: inductor and capacitor values can be chosen for a precise operating frequency and the feedback loop can be similarly tightly specified. noise generated by the circuit will always be at known frequencies. using the clkout and phsmd pins in multiphase applications the ltc3861-1 features clkout and phsmd pins that allow multiple ltc3861-1 ics to be daisychained together in multiphase applications. the clock output signal on the clkout pin can be used to synchronize additional ics in a 3-, 4-, 6- or 12- phase power supply solution feeding a single high current output, or even several outputs from the same input supply. the phsmd pin is used to adjust the phase relationship between channel 1 and channel 2, as well as the phase relationship between channel 1 and clkout, as sum- marized in table 2. the phases are calculated relative to zero degrees , defined as the rising edge of pw m 1. refer to applications information for more details on how to create multiphase applications. table 2. phase selection phsmd pin ch-1 to ch-2 phase ch-1 to clkout phase float 180 90 low 180 60 high 120 240 using the ltc3861-1 error amplifiers in multiphase applications due to the low output impedance of the error amplifiers, multiphase applications using the ltc3861-1 use one error amplifier as the master with all of the slaves error amplifiers disabled. the channel 1 error amplifier (phase = 0) may be used as the master with phases 2 through n ( up to 12) serving as slaves. to disable the slave error amplifiers connect the fb pins of the slaves to v cc . this three-states the output stages of the ampli- fiers. all comp pins should then be connected together to create pwm outputs for all phases. as noted in the section on soft-start, all track/ss pins should also be shorted together. refer to the multiphase operation sec- tion in applications information for schematics of various multiphase configurations. theory and benefits of multiphase operation multiphase operation provides several benefits over tra- ditional single phase power supplies: n greater output current capability n improved transient response n reduction in component size n increased real world operating efficiency because multiphase operation parallels power stages, the amount of output current available is n times what it o pera t ion (refer to functional diagram)
ltc3861-1 16 38611f o pera t ion (refer to functional diagram) would be with a single comparable output stage, where n is equal to the number of phases. the main advantages of polyphase operation are ripple current cancellation in the input and output capacitors, a faster load step response due to a smaller clock delay and reduced thermal stress on the inductors and mosfets due to current sharing between phases. these advantages allow for the use of a smaller size or a smaller number of components. power good indicator pins (pgood1, pgood2) each pgood pin is connected to the open drain of an internal pull- down device which pulls the pgood pin low when the corresponding fb pin voltage is outside the pgood regulation window (7.5% entering regula- tion, 10% leaving regulation). the pgood pins are also pulled low when the corresponding run pin is low, or during uvlo. when the fb pin voltage is within the 10% regulation window, the internal pgood mosfet is turned off and the pin is normally pulled up by an external resistor. when the fb pin is exiting a fault condition ( such as during normal output voltage start-up, prior to regulation), the pgood pin will remain low for an additional 30 s. this allows the output voltage to reach steady-state regulation and prevents the enabling of a heavy load from retriggering a uvlo condition. in multiphase applications, one fb pin and error amplifier are used to control all of the phases. since the fb pins for the unused error amplifiers are connected to v cc (in order to three-state these amplifiers), the pgood outputs for these amplifiers will be asserted. in order to prevent falsely reporting a fault condition, the pgood outputs for the unused error amplifiers should be left open. only the pgood output for the master control error amplifier should be connected to the fault monitor. pwm and pwmen pins the pwm pins are three-state compatible outputs, de- signed to drive mosfet drivers, drmoss, power blocks, etc., which do not represent a heavy capacitive load. an external resistor divider may be used to set the voltage to mid-rail while in the high impedance state. the pwmen outputs have an open- drain pull- up to v cc and require an appropriate external pull- down resistor. this pin is intended to drive the enable pins of the mosfet driv- ers that do not have three-state compatible pwm inputs. pwmen is low only when pw m is high impedance, and high at any other pwm state. line feedforward gain in a typical ltc3861-1 circuit, the feedback loop consists of the line feedforward circuit, the modulator, the external inductor, the output capacitor and the feedback amplifier with its compensation network. all these components affect loop behavior and need to be accounted for in the loop compensation. the modulator consists of the pwm generator, the external output mosfet drivers and the external mosfets themselves. the modulator gain varies linearly with the input voltage. the line feedforward circuit compensates for this change in gain, and provides a con- stant gain from the error amplifier output to the inductor input regardless of input voltage. from a feedback loop point of view, the combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from comp to the inductor input and has a gain roughly equal to 12v/ v. the ltc3861-1 has a wide v in and switching frequency range. the config pin is used to select the optimum range of operation for the internal multiplier, in order to maintain a constant line feedforward gain across a wide v in and switching frequency range. the config is a three- state pin and can be connected to sgnd, v cc, or floated. floating the pin externally is a valid selection as there are internal steering resistors. the selection range based on v in and switching frequency is summarized in table 3. table 3. line feedforward range selection config pin v in gnd (or) float < 14v v cc > 14v
ltc3861-1 17 38611f a pplica t ions i n f orma t ion setting the output voltage the ltc3861-1 regulates the fb pins to 0.6v. fb is con- nected to v out or v snsout ( for remote output sensing) via an external resistive divider as shown in figure 3. the divider sets the output voltage according to the following equation: v out = 0.6v ? 1 + r b r a care should be taken to place the output divider resistors and the compensation components as close as possible to the fb pin to minimize switching noise coupling into the control signal path. table 1 in the operation section shows how to connect the clkin and freq pins to choose the mode of frequency programming. the frequency of operation is given by the following equation: frequency = (r freq C 17kthz/ figure 4 shows operating frequency vs r freq . figure 3. output divider and compensation component placement comp ltc3861-1 fb r a r b v out divider and compensation components placed near fb, sgnd and comp pins c out 38611 f03 sgnd figure 4. oscillator frequency vs r freq r freq (k) 0 oscillator frequency (mhz) 40 80 100 38611 f04 0.9 2.1 2.3 2.5 0.5 1.7 1.3 0.7 1.9 0.1 0.3 1.5 1.1 20 60 120 sensing the output voltage with a differential amplifier when using the remote sense differential amplifier, care should be taken to route the v snsp and v snsn pcb traces parallel to each other all the way to the terminals of the output capacitor or remote sensing points on the board. in addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. ideally, they should be shielded by a low impedance ground plane to maintain signal integrity. when using a single ltc3861-1 to regulate two output voltages, the negative terminal of v out2 should be kelvin-connected to sgnd and the differential amplifier should be used to remotely sense v out1 . this will maxi- mize output voltage accuracy for both channels. programming the operating frequency the ltc3861-1 can be hard wired to one of two fixed fre- quencies, linearly programmed to any frequency between 250khz and 2.25 mhz or synchronized to an external clock. frequency synchronization the ltc3861-1 incorporates an internal phase-locked loop ( pll) which enables synchronization of the internal oscillator ( rising edge of pwm 1) to an external clock from 250khz to 2.25mhz. since the entire pll is internal to the ltc3861-1, simply applying a cmos level clock signal to the clkin pin will enable frequency synchronization. a resistor from freq to gnd is still required to set the free running frequency close to the sync input frequency. choosing the inductor and setting the current limit the inductor value is related to the switching frequency, which is chosen based on the trade-offs discussed in the operation section. the inductor can be sized using the following equation: l v fi v v out l out in = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 choosing a larger value of ? i l leads to smaller l, but re- sults in greater core loss ( and higher output voltage ripple
ltc3861-1 18 38611f a pplica t ions i n f orma t ion for a given output capacitance and/or esr). a reasonable starting point for setting the ripple current is 30% of the maximum output current, or: ? i l = 0.3 ? i out the inductor saturation current rating needs to be higher than the peak inductor current during transient condi- tions. if i out is the maximum rated load current, then the maximum transient current, i max , would normally be chosen to be some factor (e.g., 60%) greater than i out : i max = 1.6 ? i out the minimum saturation current rating should be set to allow margin due to manufacturing and temperature varia- tion in the sense resistor or inductor dcr. a reasonable value would be: i sat = 2.2 ? i out the programmed current limit must be low enough to ensure that the inductor never saturates and high enough to allow increased current during transient conditions and allow margin for dcr variation. for example, if: i sat = 2.2 ? i out and i max = 1.6 ? i out a reasonable i limit would be: i limit = 1.8 ? i out if the sensed inductor current exceeds current limit for 128 consecutive clock cycles, the ic will three-state the pwm outputs, reset the soft-start timer and wait 32768 switching cycles before attempting to return the output to regulation. the current limit is programmed using a resistor from the i lim pin to sgnd. the i lim pin sources 20 a to generate a voltage corresponding to the current limit. the current sense circuit has a voltage gain of 18.5 and a zero current level of 500 mv. therefore, the current limit resistor should be set using the following equation: r ilim = 18.5 ? i limit C phase ? r sense + 0.5v 20a in multiphase applications only one current limit resistor should be used per ltc3861-1. the i lim2 pin should be tied to v cc . internal logic will then cause channel 2 to use the same current limit levels as channel 1. if an ltc3861-1 has a slave and an independent, then both i lim pins must be independently set to the right voltage. inductor core selection once the value of l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core losses found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. also, core losses decrease as inductance increases. unfortunately, increased inductance requires more turns of wire, larger inductance and larger copper losses. ferrite designs have very low core loss and are preferred at high switching frequencies. however, these core materials exhibit hard saturation, causing an abrupt reduction in the inductance when the peak current capability is exceeded. do not allow the core to saturate! c in selection the input bypass capacitor in an ltc3861-1 circuit is com- mon to both channels. the input bypass capacitor needs to meet these conditions: its esr must be low enough to keep the supply drop low as the top mosfets turn on, its rms current capability must be adequate to withstand the ripple current at the input, and the capacitance must be large enough to maintain the input voltage until the input supply can make up the difference. generally, a capacitor (particularly a non-ceramic type) that meets the first two parameters will have far more capacitance than is required to keep capacitance-based droop under control. the input capacitors voltage rating should be at least 1.4 times the maximum input voltage. power loss due to esr occurs not only as i 2 r dissipation in the capacitor itself, but also in overall battery efficiency. for mobile applica- tions, the input capacitors should store adequate charge to keep the peak battery current within the manufacturers specifications. the input capacitor rms current requirement is simpli- fied by the multiphase architecture and its impact on the worst-case rms current drawn through the input network
ltc3861-1 19 38611f a pplica t ions i n f orma t ion (battery/fuse/capacitor). it can be shown that the worst- case rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used to determine the maximum rms current requirement. increasing the output current drawn from the other out- of- phase controller will actually decrease the input rms ripple current from this maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the top n - channel mosfet is approximately a square wave of duty cycle v out / v in . the maximum rms capacitor cur- rent is given by: ii v vv v rms out max out in out in () () ? this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. the total rms current is lower when both controllers are operating due to the interleav- ing of current pulses through the input capacitors. this is why the input capacitance requirement calculated above for the worst-case controller is adequate for the dual controller design. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. ceramic, tantalum, os - con and switcher- rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramics have high voltage coefficients of capacitance and may have audible piezoelectric effects; tantalums need to be surge-rated; os-cons suffer from higher inductance, larger case size and limited surface mount applicability; and electrolytics higher esr and dryout possibility require several to b e u sed. sanyo os - con svp, svpd series; sanyo poscap tqc series or aluminum electrolytic capacitors from panasonic wa series or cornell dubilier spv series, in parallel with a couple of high performance ceramic capacitors, can be used as an effective means of achieving low esr and high bulk capacitance. c out selection the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple ?v out is approximately bounded by: ? v i esr fc out l sw out + ? ? ? ? ? ? 1 8? ? where ?i l is the inductor ripple current. ?i l may be calculated using the equation: i v lf v v l out sw out in = ? ? ? ? ? ? ? ?1 since ?i l increases with input voltage, the output ripple voltage is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. manufacturers such as sanyo, panasonic and cornell du- bilier should be considered for high performance through- hole capacitors. the os-con semiconductor electrolyte capacitor available from sanyo has a good (esr)(size) product. an additional ceramic capacitor in parallel with os-con capacitors is recommended to offset the effect of lead inductance. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or transient current handling requirements of the application. aluminum elec- trolytic and dry tantalum capacitors are both available in surface mount configurations. new special polymer surface mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent output capacitor choices include the sanyo poscap tpd,
ltc3861-1 20 38611f a pplica t ions i n f orma t ion tpe, tpf series, the kemet t520, t530 and a700 series, nec/tokin neocapacitors and panasonic sp series. other capacitor types include nichicon pl series and sprague 595d series. consult the manufacturer for other specific recommendations. current sensing to maximize efficiency, the ltc3861-1 is designed to sense current through the inductors dcr, as shown in figure 5 the dcr of the inductor represents the small amount of dc winding resistance of the copper, which for most inductors applicable to this application, is between 0.3m and 1m . if the filter rc time constant is chosen to be exactly equal to the l/dcr time constant of the inductor, the voltage drop across the external capacitor is equal to the voltage drop across the inductor dcr. check the manufacturers data sheet for specifications regarding the inductor dcr in order to properly dimension the external filter components. the dcr of the inductor can also be measured using a good rlc meter. since the temperature coefficient of the inductors dcr is 3900ppm/c, first order compensation of the filter time constant is possible by using filter resistors with an equal but opposite ( negative) tc, assuming a low tc capacitor is used. that is, as the inductors dcr rises with increasing temperature, the l/dcr time constant drops. since we boost tg ltc4449 v in 12v ts v out 38611 f05a r s esl l sense resistor plus parasitic inductance filter components placed near sense pins c f ? 2r f esl/r s pole-zero cancellation v logic v cc 5v in bg gnd r f c f r f vinsns v cc pwm isnsp isnsn ltc3861-1 gnd (5a) using a resistor to sense current boost tg ltc4449 v in 12v ts v out 38611 f05b dcrl r1* inductor v logic v cc 5v in *place r1 near inductor place c1 near isnsp, isnsn pins bg gnd c1* vinsns v cc pwm isnsp isnsn ltc3861-1 gnd r1 ? c1 = l dcr (5b) using the inductor to sense current figure 5. tw o different methods of sensing current
ltc3861-1 21 38611f a pplica t ions i n f orma t ion want the filter rc time constant to match the l/dcr time constant, we also want the filter rc time constant to drop with increasing temperature. typically, the inductance will also have a small negative tc. the isnsp and isnsn pins are the inputs to the current comparators. the common mode range of the current comparators is C0.3 v to v cc C 0.5 v. continuous linear operation is provided throughout this range, allowing output voltages between 0.6 v ( the reference input to the error amplifiers) and v cc C 0.5v . the maximum output voltage is lower than v cc to account for output ripple and output overshoot. the maximum differential current sense input (v isnsp C v isnsn ) is 50mv. the high impedance inputs to the current comparators allow accurate dcr sensing. however, care must be taken not to float these pins during normal operation. filter components mutual to the sense lines should be placed close to the ltc3861-1, and the sense lines should run close together to a kelvin connection underneath the current sense element ( shown in figure 6). sensing cur- rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if low value (<5m) sense resistors are used, verify that the signal across c f resembles the current through the inductor, and reduce r f to eliminate any large step associated with the turn-on of the primary switch. if dcr sensing is used (figure 5 b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. multiphase operation when the ltc3861-1 is used in a single output, multiphase application, the slave error amplifiers must be disabled by connecting their fb pins to v cc . all current limits should be set to the same value using only one resistor to sgnd per ic. i lim2 should then be connected to v cc . these connections are shown in table 4. in a multiphase application all comp, run and track/ss pins must be connected together. table 4. multiphase configurations ch1 ch2 fb1 fb2 i lim1 i lim2 master slave on off (fb = v cc ) resistor to gnd v cc slave slave off (fb = v cc ) off (fb = v cc ) resistor to gnd v cc slave additional output off (fb = v cc ) on resistor to gnd resistor to gnd for output loads that demand high current, multiple ltc3861-1s can be daisychained to run out-of-phase to provide more output current without increasing input and output voltage ripple . the clkin pin allows the ltc3861 -1 to synchronize to the clkout signal of another ltc3861-1. the clkout signal can be connected to the clkin pin of the following ltc3861-1 stage to line up both the frequency and the phase of the entire system. tying the phsmd pin to v cc , sgnd or floating it generates a phase difference ( between clkin and clkout) of 240, 60 or 90 respectively, and a phase difference ( between ch1 and ch2) of 120, 180 or 180. figure 7 shows the phsmd connections necessary for 3-, 4-, 6- or 12-phase operation. a total of twelve phases can be daisychained to run simul- taneously out-of-phase with respect to each other. c out to sense filter, next to the controller inductor or r sense 38611 f06 figure 6. sense lines placement with inductor or sense resistor
ltc3861-1 22 38611f clkin phsmd fb1 fb2 i lim2 i lim1 fb1 fb2 i avg ltc3861-1 v cc v cc 0, 120 +240 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg 38611 f07a ltc3861-1 240, 60 clkout track/ss2 comp1 comp2 track/ss1 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3861-1 v cc v cc 0, 180 +90 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg 38611 f07b ltc3861-1 90, 270 clkout comp1 comp2 track/ss1,2 fb1 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3861-1 v cc v cc 0, 180 +60 +60 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3861-1 60, 240 clkout comp1 comp2 track/ss1,2 v cc clkin phsmd fb1 fb2 i lim2 i lim1 i avg 38611 f07c ltc3861-1 120, 300 clkout comp1 comp2 track/ss1,2 fb1 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3861-1 v cc v cc 0, 180 +60 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3861-1 60, 240 clkout comp1 comp2 track/ss1,2 v cc +60 +90 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3861-1 120, 300 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3861-1 v cc v cc 210, 30 +60 clkout comp1 comp2 track/ss1,2 clkin phsmd fb1 fb2 i lim2 i lim1 i avg ltc3861-1 270, 90 clkout comp1 comp2 track/ss1,2 v cc +60 clkin phsmd fb1 fb2 i lim2 i lim1 i avg 38611 f07d ltc3861-1-1 330, 150 clkout comp1 comp2 track/ss1,2 fb1 a pplica t ions i n f orma t ion figure 7a. 3-phase operation figure 7b. 4-phase operation figure 7c. 6-phase operation figure 7d. 12-phase operation figure 7. phsmd connections for 3-, 4-, 6- or 12-phase operation
ltc3861-1 23 38611f 38611 f08 sw1 v i cin i cout single phase sw1 v sw2 v i cin i l2 i l1 i cout dual phase ripple figure 8. single and 2-phase current waveforms duty factor (v out /v in ) 0.1 di c(p-p) v o /l 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.3 0.5 0.6 38611 f09 0.2 0.4 0.7 0.8 0.9 1 phase 2 phase figure 9. normalized output ripple current vs duty factor [i rms 0.3 (di c(pp) )] 0 0.1 0.2 0.3 0.4 38611 f10 0.5 0.6 duty factor (v out /v in ) 0.1 rms input ripple current dc load current 0.3 0.5 0.6 0.2 0.4 0.7 0.8 0.9 1 phase 2 phase figure 10. normalized rms input ripple current vs duty factor for 1 and 2 output stages a pplica t ions i n f orma t ion a multiphase power supply significantly reduces the amount of ripple current in both the input and output ca- pacitors. the rms input ripple current is divided by, and the effective ripple frequency is multiplied by, the number of phases used ( assuming that the input voltage is greater than the number of phases used times the output volt- age). the output ripple amplitude is also reduced by the number of phases used. figure 8 graphically illustrates the principle. the worst-case rms ripple current for a single stage design peaks at an input voltage of twice the output volt- age. the worst case rms ripple current for a two stage design results in peak outputs of 1/4 and 3/4 of input voltage. when the rms current is calculated, higher ef- fective duty factor results and the peak current levels are divided as long as the current in each stage is balanced. refer to application note 19 for a detailed description of how to calculate rms current for the single stage switching regulator. figures 9 and 10 illustrate how the input and output currents are reduced by using an additional phase. for a 2-phase converter , the input current peaks drop in half and the frequency is doubled. the input capacitor requirement is thus reduced theoretically by a factor of four! just imagine the possibility of capacitor savings with even higher number of phases!
ltc3861-1 24 38611f output current sharing when multiple ltc3861-1s are daisychained to drive a common load, accurate output current sharing is essential to achieve optimal performance and efficiency. otherwise, if one stage is delivering more current than another, then the temperature between the two stages will be different, and that could translate into higher switch r ds(on) , lower efficiency, and higher rms ripple. when the comp and i avg pins of multiple ltc3861-1s are tied together, the amount of output current delivered from each ltc3861-1 is actively balanced by the i avg loop. the sgnd pins of the multiple ltc3861-1s must be kelvined to the same point for optimal current sharing. dual-channel operation the ltc3861-1 can control two independent power supply outputs with no channel-to-channel interaction or jitter. the following recommendations will ensure maximum performance in this mode of operation: n the output of each channel should be sensed using the differential sense amplifier. the sgnd pins and exposed pad and all local small-signal gnd should then be a kelvin connection to the negative terminal of each channel output. this will provide the best possible regulation of each channel without adversely affecting the other channel. n due to internal logic used to determine the mode of operation, separate current limit resistors should be used for each channel in dual-channel operation, even when the values are the same. a pplica t ions i n f orma t ion table 5 shows the i lim and ea configuration for dual- channel operation. table 5. dual-channel configuration ch1 ch2 ea1 ea2 i lim1 i lim2 independent independent on on resistor to gnd resistor to gnd tracking and soft-start (track/ss pins) the start-up of the supply output is controlled by the volt- age on the track/ss pin for that channel. the ltc3861-1 regulates the fb pin voltage to the lower of the voltage on the track/ss pin and the internal 600 mv reference. the track/ss pin can therefore be used to program an external soft-start function or allow the output supply to track another supply during start-up. external soft-start is enabled by connecting a capacitor from the track/ss pin to sgnd. an internal 2.5 a cur- rent source charges the capacitor, creating a linear voltage ramp at the track/ss pin, and causing the output sup- ply to rise smoothly from its prebiased value to its final regulated value. the total soft-start time is approximately: t ss (milliseconds) = c ss f ? 600mv 2.5a alternatively, the track/ss pin can be used to track another supply during start-up.
ltc3861-1 25 38611f for example, figure 11 shows the start-up of v out2 controlled by the voltage on the track/ ss2 pin. nor - mally this pin is used to allow the start-up of v out2 to track that of v out1 as shown qualitatively in figures 12a and 12 b. when the voltage on the track/ss2 pin is less than the internal 0.6 v reference, the ltc3861-1 regulates the fb2 voltage to the track/ss2 pin voltage instead of 0.6 v. the start-up of v out2 may ratiometrically track that of v out1 , according to a ratio set by a resistor divider (figure 12b): v v ra r rr rb r out out tracka tracka trackb 1 2 2 22 = + + ? aa for coincident tracking (v out1 = v out2 during start-up), r2a = r tracka r2b = r trackb a pplica t ions i n f orma t ion the ramp time for v out2 to rise from 0 v to its final value is: tt v rr r ss ss out f tracka trackb tracka 21 1 06 = + ? . ? for coincident tracking, tt v v ss ss out f out f 21 2 1 = ? where v out1f and v out2f are the final, regulated values of v out1 and v out2 . v out1 should always be greater than v out2 when using the track/ss2 pin for tracking. if no tracking function is desired, then the track/ss2 pin may be tied to a capacitor to ground, which sets the ramp time to final regulated output voltage. it is only possible to track another supply that is slower than the internal soft-start ramp. at the completion of tracking, the track/ss pin must be >620 mv, so as not to affect regulation accuracy and to ensure the part is in ccm mode. ltc3861-1 fb2 v out2 v out1 fb1 track/ss2 r2b r2a 38611 f11 r1b r1a r tracka r trackb figure 11. using the track/ss pin time (12a) coincident tracking v out1 v out2 output voltage time 38611 f12b (12b) ratiometric tracking v out1 v out2 output voltage figure 12. tw o different modes of output voltage tracking
ltc3861-1 26 38611f a pplica t ions i n f orma t ion feedback loop compensation the ltc3861-1 is a voltage mode controller with a second dedicated current sharing loop to provide excellent phase- to-phase current sharing in multiphase applications. the current sharing loop is internally compensated. while type 2 compensation for the voltage control loop may be adequate in some applications ( such as with the use of high esr bulk capacitors), type 3 compensation, along with ceramic capacitors, is recommended for opti- mum transient response. referring to figure 13, the error amplifiers sense the output voltage at v out . the positive input of the error amplifier is connected to an internal 600 mv reference, while the negative input is connected to the fb pin. the output is connected to comp, which is in turn connected to the line feedforward circuit and from there to the pwm generator. to speed up the overshoot recovery time, the maximum potential at the comp pin is internally clamped. unlike many regulators that use a transconductance (g m ) amplifier, the ltc3861-1 is designed to use an inverting summing amplifier topology with the fb pin configured as a virtual ground. this allows the feedback gain to be tightly controlled by external components, which is not possible with a simple g m amplifier. in addition, the voltage feedback amplifier allows flexibility in choosing pole and zero locations. in particular, it allows the use of type 3 compensation, which provides a phase boost at the lc pole frequency and significantly improves the control loop phase margin. in a typical ltc3861-1 circuit, the feedback loop consists of the line feedforward circuit, the modulator, the external inductor, the output capacitor and the feedback amplifier with its compensation network. all these components affect loop behavior and need to be accounted for in the loop compensation. the modulator consists of the pwm generator, the output mosfet drivers and the external mosfets themselves. the modulator gain varies linearly with the input voltage. the line feedforward circuit com- pensates for this change in gain, and provides a constant gain from the error amplifier output to the inductor input regardless of input voltage. from a feedback loop point of view, the combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from comp to the inductor input. it has fairly benign ac behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. the external inductor/ output capacitor combination makes a more significant contribution to loop behavior. these components cause a second order lc roll-off at the output with 180 phase shift. this roll-off is what filters the pwm waveform, resulting in the desired dc output voltage, but this phase shift causes stability issues in the feedback loop and must be frequency compensated. at higher frequencies, the reactance of the output capacitor will approach its esr, and the roll-off due to the capacitor will stop, leaving C20db/decade and 90 of phase shift. figure 13 shows a type 3 amplifier. the transfer function of this amplifier is given by the following equation: v v sc r s r r c sr c c comp out = + () ++ [] + ( ? () 1 12 1 1 3 3 11 2 )) + ? ? ? ? + () 1 1 2 2 1 33 s c c r sc r ( // ) ? + v out v ref r1 r3 c3 r2 c1 gain (db) c2 fb comp freq ?1 ?1 +1 gain phase boost 0 phase (deg) ?90 ?180 ?270 ?380 38611 f13 figure 13. type 3 amplifier compensation
ltc3861-1 27 38611f a pplica t ions i n f orma t ion the rc network across the error amplifier and the feed- forward components r3 and c3 introduce two pole-zero pairs to obtain a phase boost at the system unity-gain frequency, f c . in theory, the zeros and poles are placed symmetrically around f c , and the spread between the zeros and the poles is adjusted to give the desired phase boost at f c . however, in practice, if the crossover frequency is much higher than the lc double-pole frequency, this method of frequency compensation normally generates a phase dip within the unity bandwidth and creates some concern regarding conditional stability. if conditional stability is a concern, move the error ampli- fiers zero to a lower frequency to avoid excessive phase dip. the following equations can be used to compute the feedback compensation components value: f switching frequency f lc f r sw lc out esr = = = 1 2 1 2 e esr out c choose: f crossover frequency f ff c sw z err lc == == 10 1 2 1( ) r rc f f r rc ff z res c p err esr 21 5 1 2 1 33 2 1 () () == + () = == == 1 2 21 2 5 1 2 33 2 rc c ff rc p res c ( // ) () required error amplifier gain at frequency f c : a + ? ? ? ? ? ? + ? ? ? ? ? ? 40 1 20 1 2 22 log ? log ? f f f f c lc c esr 00 20 2 1 11 2 log log ? ( a r r f f f mod lc c p re () + ? ? ? ? ? ? + ss c p res z res z res c e f ff f f f ) () () () ? + ? ? ? ? ? ? + 22 2 1 s sr lc esr lc p res c f ff f f + ? ? ? ? ? ? + ? ? ? ? ? ? ? () 1 2 where amod is the modulator and line feedforward gain and is equal to: a mod v in(max) ? dc max v ramp 12v/ v where dc max is the maximum duty cycle and v ramp is the line feedforward compensated pwm ramp voltage. once the value of resistor r1, poles and zeros location have been decided, the value of r2, c1, c2, r3 and c3 can be obtained from the previous equations. compensating a switching power supply feedback loop is a complex task. the applications shown in this data sheet show typical values, optimized for the power components shown. though similar power compon- ents should suffice, substantially changing even one major power component may degrade performance significantly. stability also may depend on circuit board layout. to verify the calculated component values, all new circuit designs should be prototyped and tested for stability.
ltc3861-1 28 38611f a pplica t ions i n f orma t ion inductor the inductor in a typical ltc3861-1 circuit is chosen for a specific ripple current and saturation current. given an input voltage range and an output voltage, the inductor value and operating frequency directly determine the ripple current. the inductor ripple current in the buck mode is: = ? ? ? ? ? ? i v fl v v l out out in ( )( ) ?1 lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. thus highest efficiency operation is obtained at low frequency with small ripple current. to achieve this however, requires a large inductor. a reasonable starting point is to choose a ripple cur- rent between 20% and 40% of i o(max) . note that the largest ripple current occurs at the highest v in . to guar- antee that ripple current does not exceed a specified maximum, the inductor in buck mode should be chosen according to: l v fi v v out l max out in max ? ? ? ? ? ? () () ?1 power mosfet selection the ltc3680 requires at least two external n- channel power mosfets per channel, one for the top ( main) switch and one or more for the bottom ( synchronous) switch. the number, type and on-resistance of all mosfets selected take into account the voltage step-down ratio as well as the actual position ( main or synchronous) in which the mosfet will be used. a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output voltage that is less than one-third of the input voltage. in applications where v in >> v out , the top mosfets on-resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300khz. mosfet manufacturers have designed special purpose devices that provide reasonably low on-resistance with significantly reduced input capacitance for the main switch application in switching regulators. selection criteria for the power mosfets include the on- resistance r ds(on) , input capacitance, breakdown voltage and maximum output current. for maximum efficiency, on-resistance r ds(on) and input capacitance should be minimized. low r ds(on) minimizes conduction losses and low input capacitance minimizes switching and transition losses. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (figure 14). the curve is generated by forcing a constant-input cur- rent into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage figure 14. gate charge characteristic + ? v ds v in v gs miller effect q in a b c miller = (q b ? q a )/v ds v gs v + ? 38611 f14
ltc3861-1 29 38611f a pplica t ions i n f orma t ion across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage specified. c miller is the most important se- lection criteria for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets. c rss and c os are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous s out in = w witch duty cycle vv v in out in C = the power dissipation for the main and synchronous mosfets at maximum output current are given by: p v v ir v i main out in max ds on in max = () ++ 2 2 1 2 () ( () r rc vv v dr miller cc th il th il )( ) ? ? () () 11 + ? ? ? ? ? ? ? ?? = ? + () ( )( ) () f p vv v ir sync in out in max ds n 2 0 1 where is the temperature dependency of r ds(on) , r dr is the effective top driver resistance, v in is the drain po- tential and the change in drain potential in the particular application. v th(il) is the data sheet specified typical gate threshold voltage specified in the power mosfet data sheet at the specified drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique previously described. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds( on) vs temperature curve. typical values for range from 0.005/ c to 0.01/ c depending on the particular mosfet used. multiple mosfets can be used in parallel to lower r ds( on) and meet the current and thermal requirements if desired. suitable drivers such as the ltc4449 are capable of driving large gate capacitances without sig- nificantly slowing transition times. in fact, when driving mosfets with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (5 or less) to reduce noise and emi caused by the fast transitions mosfet driver selection gate driver ics, drmoss and power blocks with an interface compatible with the ltc3861-1 s three- state pwm outputs or the ltc3861-1 s pwm / pwmen outputs can be used.
ltc3861-1 30 38611f a pplica t ions i n f orma t ion efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% - (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the system produce losses, three main sources usually account for most of the losses in ltc3861-1 applications : 1) i 2 r losses , 2) topside mosfet transition losses, 3) gate drive current. 1. i 2 r losses occur mainly in the dc resistances of the mosfet, inductor, pcb routing, and input and output capacitor esr. since each mosfet is only on for part of the cycle, its on-resistance is effectively multiplied by the percentage of the cycle it is on. therefore in high step- down ratio applications the bottom mosfet should have a much lower r ds(on) than the top mosfet. it is crucial that careful attention is paid to the layout of the power path on the pcb to minimize its resistance. in a 2-phase, 1.2 v output, 60 a system, 1 m of pcb resistance at the output costs 5% in efficiency. 2. transition losses apply only to the topside mosfet but in 12 v input applications are a very significant source of loss. they can be minimized by choosing a driver with very low drive resistance and choosing a mosfet with low q g , r g and c rss . 3. gate drive current is equal to the sum of the top and bottom mosfet gate charges multiplied by the fre- quency of operation. however, many drivers employ a linear regulator to reduce the input voltage to a lower gate drive voltage. this multiplies the gate loss by that step down ratio. in high frequency applications it may be worth using a secondary user supplied rail for gate drive to avoid the linear regulator. other sources of loss include body or schottky diode conduction during the driver dependent non-overlap time and inductor core losses. design example as a design example, consider a 2- phase application where v in = 12 v, v out = 1.2 v, i load = 60 a and f switch = 300khz. assume that a secondary 5 v supply is available for the ltc3861-1 v cc supply. the inductance value is chosen based on a 25% ripple assumption. each channel supplies an average 30 a to the load resulting in 7.7a peak-peak ripple: i v v v fl l out out in = ? ? ? ? ? ? ?C ? 1 a 470 nh inductor per phase will create 7.7 a peak-to- peak ripple. a 0.47 h inductor with a dcr of 0.67 m typical is selected from the w rth 744355147 series. float clkin and connect 28 k from freq to sgnd for 300khz operation. setting i limit = 54 a per phase leaves plenty of headroom for transient conditions while still adequately protecting against inductor saturation. this corresponds to: r ilim = 18.5 ? 54a ? 0.67m ? + 0.53v 20a = 58.5k ? choose 59k. for the dcr sense filter network, we can choose r = 2.87k and c = 220nf to match the l/ dcr time constant of the inductor. a loop crossover frequency of 45 khz provides good tran- sient performance while still being well below the switching frequency of the converter. six 330f 9 m poscaps and four 100 f ceramic capacitors are chosen for the output capacitors to maintain supply regulation during severe transient conditions and to minimize output voltage ripple. the following compensation values (figure 13) were determined empirically: r1 = 10k r2 = 5.9k r3 = 280 c1 = 4.7nf c2 = 100pf c3 = 3.3nf
ltc3861-1 31 38611f to set the output voltage equal to 1.2v: r fb1 = 10k, r fb2 = 10k the ltc4449 gate driver and external mosfets are chosen for the power stage. drmoss from fairchild, infineon, vishay and others can also be used. printed circuit board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the converter. 1. the connection between the sgnd pin on the ltc3861-1 and all of the small-signal components surrounding the ic should be isolated from the system power ground. place all decoupling capacitors, such as the ones on v cc , between isnsp and isnsn etc., close to the ic. in multiphase operation sgnd should be kelvin- connected to the main ground node near the bottom terminal of the input capacitor. in dual-channel operation, sgnd should be kelvin-connected to the bottom terminal of the output capacitor for channel 2, and channel 1 should be remotely sensed using the remote sense differential amplifier. 2. place the small-signal components away from high fre- quency switching nodes on the board. the ltc3861-1 contains remote sensing of output voltage and inductor current and logic-level pwm outputs enabling the ic to be isolated from the power stage. 3. the pcb traces for remote voltage and current sense should avoid any high frequency switching nodes in the circuit and should ideally be shielded by ground planes. each pair ( v snsp and v snsn , i snsp and i snsn ) should be routed parallel to one another with minimum spacing between them. if dcr sensing is used, place the top resistor (figure 5 b, r1) close to the switching node. 4. the input capacitor should be kept as close as possible to the power mosfets. the loop from the input capaci- tors positive terminal, through the mosfets and back to the input capacitors negative terminal should also be as small as possible. 5. if using discrete drivers and mosfets, check the stress on the mosfets by independently measuring the drain- to- source voltages directly across the device terminals. beware of inductive ringing that could exceed the maximum voltage rating of the mosfet. if this ringing cannot be avoided and exceeds the maximum rating of the device, choose a higher voltage rated mosfet. 6. when cascading multiple ltc3861-1 ics, minimize the capacitive load on the clkout pin to minimize phase error. kelvin all the ltc3861-1 ic grounds to the same point, typically sgnd of the ic containing the master. a pplica t ions i n f orma t ion
ltc3861-1 32 38611f typical a pplica t ions dual phase 1.2v/45a converter with delta 45a power block, f sw = 400khz 1.5v/30a and 1.2v/30a converter with discrete gate drivers and mosfets, f sw = 300khz v out 1.2v/ 45a c out1 100f 4 6.3v 22f 16v 22f 16v 22f 16v 22f 16v c out2 : sanyo 2r5tpe330m9 c out1 : murata grm32er60j107me20 c out2 330f 6 2.5v 0.22f 0.22f 30.9k v cc v cc 45.3k 1.69k 1.5nf ltc3861-1 fb1 comp1 vsnsp vsnsn vsnsout comp2 fb2 +cs1 v in1 pwm1 gnd pwm2 v in2 +cs2 ? cs1 gnd v out1 +7v v out2 gnd ? cs2 run1 i lim1 sgnd isns1p isns1n isns2n isns2p sgnd i lim2 run2 v cc ss1 vinsns config i avg pgood1 pwmen1 pwm1 ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 run1 run1 v cc v out v cc 5v 100k 110 6.8nf 150pf 10k 10k 1 f v in 7v to 14v temp1 temp2 d12s1- r845a ss1 ss1 v in c in 180f 38611 ta02 100pf 4.7f v out1 1.5v/ 30a c out1 100f 2 6.3v c out2 , c out4 : sanyo 2r5tpe330m9 c out1 , c out3 : murata grm32er60j107me20 l1, l2 : wrth elektronik 744355147 c in2 22f 2 v out2 1.2v/ 30a c out3 100f 2 6.3v c out4 330f 3 2.5v c out2 330f 3 2.5v c in3 22f 2 27.4k 61.9k 3.92k 2.2nf ltc3861-1 fb1 comp1 vsnsp vsnsn vsnsout comp2 fb2 run1 i lim1 sgnd isns1p isns1n isns2n isns2p sgnd i lim2 run2 v cc ss1 vinsns config i avg pgood1 pwmen1 pwm1 ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 run1 run2 v cc v out1 v out2 v cc 5v 100k 499 2.2nf 100pf 30.1k 0.1f 1 f v in 7v to 14v ltc4449 in v cc l1 0.47h l2 0.47h d1 0.22f 0.22f 2.87k m2 2.87k v cc 100k 0.047f 3.57k 2.2nf 499 2.2nf 100pf 20k 20k 20k v in 4.7f v logic v cc boost gnd tg ts bg c in1 180f 38611 ta03 0.22f bsc010ne2ls 2 m1 bsc050ne2ls 2 ltc4449 in v cc d2 m4 v in 4.7f v logic v cc boost gnd tg ts bg 0.22f bsc010ne2ls 2 m3 bsc050ne2ls 2 61.9k
ltc3861-1 33 38611f 4-phase 1v/100a converter with drmos, f sw = 500khz typical a pplica t ions c out2 330f 8 2.5v v out 1v/ 100a c out1 100f 8 6.3v 34k v cc 38611 ta04 53.6k 5.62k 3.3nf ltc3861-1 fb1 comp1 vsnsp vsnsn vsnsout comp2 fb2 run1 i lim1 sgnd isns1p isns1n isns2n isns2p sgnd i lim2 run2 v cc ss1 vinsns config i avg pgood1 pwmen1 pwm1 ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 run1 run1 v cc i avg1 ss1 v out v cc 5v 100k 100pf 280 3.3nf 470pf 20k 30.1k 0.1f c in1 180f v in 7v to 14v 10k clkin 500khz external sync input ss1 ss1 v in disb pwm vdrv vcin vswh pgnd tda21220 boot phase smod v in disb pwm vdrv vcin smod cgnd v cc v in 1 0.22f l1 0.47h l2 0.47h 10k 10k vswh pgnd tda21220 boot phase cgnd v cc v in 1 0.22f 10k 0.22f 0.22f 2.87k 2.87k v cc v cc 34k c in5 22f 2 16v c in3 22f 2 16v c in4 22f 2 16v v cc ltc3861-1 fb1 comp1 vsnsp vsnsn vsnsout comp2 fb2 run1 i lim1 sgnd isns1p isns1n isns2n isns2p sgnd i lim2 run2 v cc ss1 vinsns config i avg pgood1 pwmen1 pwm1 ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 run1 run2 v cc 5v 1 f v in 10k vswh pgnd tda21220 boot phase cgnd v cc v in 1 0.22f l3 0.47h l4 0.47h 10k 10k vswh pgnd tda21220 boot phase cgnd v cc v in 1 0.22f 10k 0.22f 0.22f 2.87k 2.87k ss1 v cc c in2 22f 2 16v 2.2f 16v 2.2f 16v 2.2f 16v 2.2f 16v 2.2f 16v 2.2f 16v 2.2f 16v 2.2f 16v v in disb pwm vdrv vcin smod v in disb pwm vdrv vcin smod 1 f c out2 : sanyo 2r5tpe330m9 c out1 : murata grm32er60j107me20 l1, l2, l3, l4 : wrth elektronik 744355147 53.6k
ltc3861-1 34 38611f dual-output converter: triple phase + single phase with drmos, synchronized to an external 500khz clock typical a pplica t ions c out2 330f 6 2.5v v out1 1v/ 75a c out1 100f 6 6.3v c out4 330f 3 2.5v v out2 1.8v/ 25a c out3 100f 2 6.3v 34k v cc 38611 ta05 53.6k 3.48k 3.3nf ltc3861-1 fb1 comp1 vsnsp vsnsn vsnsout comp2 fb2 run1 i lim1 sgnd isns1p isns1n isns2n isns2p sgnd i lim2 run2 v cc ss1 vinsns config i avg pgood1 pwmen1 pwm1 ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 run1 run1 v cc v cc v out1 v out2 v cc 5v 100k 100pf 280 3.3nf 150pf 20k 30.1k 0.1f 1 f v in 7v to 14v ss1 clkin 500khz external sync input ss1 ss1 vswh pgnd fdmf6707b boot phase cgnd v cc 2.2f 16v 1 0.22f l1 0.47h l2 0.47h 10k vswh pgnd fdmf6707b boot phase cgnd v cc 2.2f 16v 1 0.22f 10k 0.22f 0.22f 2.87k 2.87k v cc 34k 100k 2.1k 1.5nf ltc3861-1 fb1 comp1 vsnsp vsnsn vsnsout comp2 fb2 run1 i lim1 sgnd isns1p isns1n isns2n isns2p sgnd i lim2 run2 v cc ss1 vinsns config i avg pgood1 pwmen1 pwm1 ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 run1 run2 v cc 5v 280 3.3nf 100pf 10k 1 f v in vswh pgnd fdmf6707b boot phase cgnd v cc 2.2f 16v 1 0.22f l3 0.47h l4 0.47h 10k vswh pgnd fdmf6707b boot phase cgnd v cc 2.2f 16v 1 0.22f 10k 0.22f 0.22f 2.87k 2.87k 0.1f v cc 10k v in 2.2f 16v 10k v in 2.2f 16v c in5 22f 2 16v c in3 22f 2 16v c in4 22f 2 16v 10k v in 2.2f 16v 10k v in 2.2f 16v c in2 22f 2 16v v in disb pwm vdrv vcin smod v in disb pwm vdrv vcin smod v in disb pwm vdrv vcin smod v in disb pwm vdrv vcin smod c in1 180f c out2 , c out4 : sanyo 2r5tpe330m9 c out1 , c out3 : murata grm32er60j107me20 l1, l2, l3, l4 : wrth elektronik 744355147 4.99k 53.6k 53.6k
ltc3861-1 35 38611f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d)
ltc3861-1 36 38611f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0812 printed in usa r ela t e d p ar t s part number description comments ltc3880/ ltc3880-1 dual output polyphase step-down dc/dc controller with digital power system management v in up to 24v, 0.5v v out 5.5v, analog control loop, i 2 c/pmbus interface with eeprom and 16-bit adc ltc3855 dual output, 2-phase, synchronous step-down dc/dc controller with diffamp and dcr temperature compensation 4.5v v in 38v, 0.8v v out 12v, pll fixed frequency 250khz to 770khz ltc3856 single output 2-phase synchronous step-down dc/dc controller with diffamp and dcr temperature compensation 4.5v v in 38v, 0.8v v out 5v, pll fixed 250khz to 770khz frequency ltc3838 dual output, 2-phase, synchronous step-down dc/dc controller with diff amp and controlled on-time 4.5v v in 38v, 0.8v v out 5.5v, pll, up to 2mhz switching frequency ltc3839 single output, 2-phase, synchronous step-down dc/dc controller with diff amp and controlled on-time 4.5v v in 38v, 0.8v v out 5.5v, pll, up to 2mhz switching frequency ltc3860 dual, multiphase, synchronous step-down dc/dc controller with diffamp and three-state output drive operates with power blocks, drmos devices or external mosfets, 3v v in 24v, t on(min) = 20ns ltc3869/ ltc3869-2 dual output, 2-phase synchronous step-down dc/dc controller, with accurate current share 4v v in 38v, v out3 up to 12.5v, pll fixed 250khz to 750khz frequency ltc3866 single output, high power, current mode controller with submilliohm dcr sensing 4.75v v in 38v, 0.6v v out 3.5v, fixed 250khz to 770khz frequency ltc4449 high speed synchronous n-channel mosfet driver v in up to 38v, 4v v cc 6.5v, adaptive shoot-through protection, 2mm 3mm dfn-8 package ltc4442/ LTC4442-1 high speed synchronous n-channel mosfet driver v in up to 38v, 6v v cc 9v adaptive shoot-through protection, msop-8 package ltc3861 dual, multiphase, synchronous step-down dc/dc controller with tw o diffamps and three-state output drive operates with power blocks, drmos devices or external mosfets, 3v v in 24v, t on(min) = 20ns t ypical applica t ion dual phase 1.2v/60a converter with discrete gate drivers and mosfets, f sw = 300khz v out 1.2v/ 60a c out1 100f 4 6.3v c out2 : sanyo 2r5tpe330m9 c out1 : murata grm32er60j107me20 l1, l2 : wrth elektronik 744355147 c in2 22f 2 c out2 330f 6 2.5v c in3 22f 2 28.7k v cc v cc 59k 13k 1nf ltc3861-1 fb1 comp1 vsnsp vsnsn vsnsout comp2 fb2 run1 i lim1 sgnd isns1p isns1n isns2n isns2p sgnd i lim2 run2 v cc ss1 vinsns config i avg pgood1 pwmen1 pwm1 ss2 freq clkin clkout phsmd pgood2 pwmen2 pwm2 run1 run1 v cc v out v cc 5v 100k 221 1nf 220pf 20k 20k 1 f v in 7v to 14v ltc4449 in v cc l1 0.47h l2 0.47h d1 0.22f 0.22f 2.87k m2 2.87k ss1 ss1 v in 4.7f v logic v cc boost gnd tg ts bg c in1 180f 38611 ta06 0.22f bsc010ne2ls 2 m1 bsc050ne2ls 2 ltc4449 in v cc d2 m4 v in 4.7f v logic v cc boost gnd tg ts bg 0.22f bsc010ne2ls 2 m3 bsc050ne2ls 2 100pf

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